circuit technology www.aeroflex.com eroflex circuit technology - advanced multichip modules ? scd3750 rev a 8/31/98 pin description a 0?9 address inputs i/o 0-15 data input / output we read/write enable oe output enable ras row address strobe ucas upper byte control / column address strobe lcas lower byte control / column address strobe v c c +5.0v power supply v ss ground nc not connected features n fast access time (t r a c ): 70ns n power supply: 5.0v 0.5v n packaging l 42 lead plastic surface-mount soj (l4) n industrial and military temperature ranges n three-state unlatched output n fast page mode n ras -only refresh n xcas before ras refresh n hidden refresh n 1024 cycle refresh in 16ms n low power dissipation n long refresh period option act?pd1m16 fast page mode 16 megabit plastic monolithic dram f i e i d c e r t a e r o f l e x l a b s i n c . iso 900 1 v s s i/o15 i/o14 i/o13 i/o12 v s s i/o11 i/o10 i/o9 i/o8 nc lcas ucas oe a9 a8 a7 a6 a5 a4 v s s vcc i/o0 i/o1 i/o2 i/o3 vcc i/o4 i/o5 i/o6 i/o7 nc nc we ras nc nc a0 a1 a2 a3 vcc 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 pin configuration top view
aeroflex circuit technology scd3750 rev a 8/31/98 plainview ny (516) 694-6700 2 absolute maximum ratings symbol parameter minimum maximum units t c case operating temp. -55 +125 c t stg storage temperature -55 +150 c i os short circuit output current - 50 ma p t power dissipated - 1 w v cc supply voltage range -1.0 +7.0 v v t voltage range on any pin* -1.0 +7.0 v stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute-maximum rated conditions for extended periods may affect device reliability. * all voltage values are with respect to vss. recommended operating conditions symbol parameter minimum maximum units v cc power supply voltage +4.5 +5.5 v v ih input high voltage +2.4 - v v il input low voltage - +0.8 v t cm operating temp. (mil) -55 +125 c t ci operating temp. (ind.) -40 +85 c capacitance (v in = 0v, f = 1mhz, tc = 25c ) symbol parameter maximum units c i(a) a 0-9 input capacitance 10 pf c i(rc) ras and cas input capacitance 10 pf c i(oe) oe input capacitance 10 pf c i(we) we input capacitance 10 pf c o output capacitance 15 pf these parameters are guaranteed by design but not tested. dc characteristics (v c c = 5.0v, v s s = 0v, t c i or t c m ) parameter sym conditions min max units output low voltage v ol i ol = 4.2 ma - 0.4 v output high voltage v oh i oh = -5 ma 2.4 v input leakage current i l v i =0to+6.5v, all others 0v to v cc -10 +10 a output leakage current i o v o =0tov cc, cas high -10 +10 a read or write cycle current 1,2 i cc1 v cc = 5.5v, minimum cycle 190 ma
aeroflex circuit technology scd3750 rev a 8/31/98 plainview ny (516) 694-6700 3 standby current i cc2 vih = 2.4v (ttl), after 1 memory cycle, ras and cas high - 2 ma i cc3 vih = vcc - 0.05v (cmos), after 1 memory cycle, ras and cas high - 1 ma average page current 2 i cc4 ras low, cas cycling - 100 ma 1. measured with a maximum of one address change while ras = v i l . 2. measured with a maximum of one address change while cas = v i h . ac characteristics * (v c c = 5.0v 10%, v s s = 0v, t c i or t c m ) parameter sym min max units access time from column-address t a a - 35 ns cas low access time from cas t c a c - 20 ns column access time from cas precharge t c p a - 40 ns access time from ras t r a c - 70 ns oe access time t o e a - 20 ns output buffer turn-off delay 1 t o f f 0 15 ns output buffer turn-off delay time from oe 1 t o e z 0 15 ns * valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when cas goes low. 1. t o f f and t o e z are specified when the outputs are no longer driven. the outputs are disabled by bringing either oe or cas high. ac characteristics (v c c = 5.0v, v s s = 0v, t c i or t c m ) parameter sym min max units cycle time, read or write random 1 t r c 130 - ns cycle time, fast page mode read or write 1,2 t p c 45 - ns cycle time, fast page mode read-modify-write 1 t p r w c 90 - ns pulse duration, ras low fast page mode 3 t r a s p 70 200,000 ns pulse duration, ras low nonpage mode 3 t r a s 70 10,000 ns pulse duration, cas low 4 t c a s 20 10,000 ns pulse duration, cas high precharge time t c p 10 - ns pulse duration, ras high precharge time t r p 50 - ns pulse duration, we low t w p 15 - ns setup time, column address before cas low t a s c 0 - ns setup time, row address before ras low t a s r 0 - ns setup time, data 5 t d s 0 - ns setup time, we high before cas low t r c s 0 - ns setup time, we low before cas high t c w l 20 - ns setup time, we low before ras high t r w l 20 - ns dc characteristics (continued) (v c c = 5.0v, v s s = 0v, t c i or t c m ) parameter sym conditions min max units
aeroflex circuit technology scd3750 rev a 8/31/98 plainview ny (516) 694-6700 4 setup time, we low before cas low (early-write operation only) t w c s 0 - ns hold time, column address after cas low t c a h 15 - ns hold time, data 5 t d h 15 - ns hold time, row address after ras low t r a h 10 - ns hold time, we high after cas high 6 t r c h 0 - ns hold time, we high after ras high 6 t r r h 0 - ns 1. all cycle times assume t t = 5ns, reference to v i h (min) and v i l (max). 2. to assume t p c min, t a s c should be 3 t c p . 3. in read-write cycle, t r w d and t r w l must be observed. 4. in read-write cycle, t c w d and t c w l must be observed. 5. referenced to the later of xcas or we in write operations. 6. either t r r h or t r c h must be satisfied for a read cycle. ac characteristics (v c c = 5.0v, v s s = 0v, t c i or t c m ) parameter sym min max units we low before cas low hold time (early-write operation only) t w c h 15 - ns oe command hold time t o e h 15 - ns ras referenced to oe hold time t r o h 10 - ns ras from cas precharge (fast page mode) t r h c p 40 - ns column address to we low delay time (read-write operation only) t a w d 60 - ns ras low to cas high delay time (cbr refresh only) t c h r 15 - ns cas high to ras low delay time ( cas to ras precharge time) t c r p 5 - ns ras low to cas high delay time ( cas hold time) t c s h 70 - ns cas low to ras low delay time ( cas set-up time) t c s r 5 - ns cas low to we low delay time (read-write operation only) t c w d 45 - ns oe to data delay time t o e d 15 - ns ras low to column address delay time 1 t r a d 15 35 ns column address to ras high delay time t r a l 35 - ns ras low to cas low delay time 1 t r c d 20 50 ns ras high to cas low precharge time t r p c 5 - ns cas low to ras high delay time ( ras hold time) t r s h 20 - ns ras low to we low delay time (read-write operation only) t r w d 95 - ns we low after cas precharge delay time (read-write operation only) t c w d 65 - ns refresh time interval t r e f 16 ms transition time 2 t t 3 50 ns 1. the maximum value is specified only to assure access time 2. transition times (rise and fall) for ras and xcas are to be a minimum of 3ns and a maximum of 30ns. ac characteristics (continued) (v c c = 5.0v, v s s = 0v, t c i or t c m ) parameter sym min max units
aeroflex circuit technology scd3750 rev a 8/31/98 plainview ny (516) 694-6700 5 i o l parameter typical units input pulse level 0 ? 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v notes: 1) v z is programmable from -2v to +7v. 2) i o l and i o h programmable from 0 to 16 ma. 3) tester impedance z o =75 w. 4) v z is typically the midpoint of v o h and v o l . 5) i o l and i o h are adjusted to simulate a typical resistance load circuit. 6) ate tester includes jig capacitance. i o h to device under test v z ~ 1.5 v (bipolar supply) current source current source c l = 50 pf ac test circuit
aeroflex circuit technology scd3750 rev a 8/31/98 plainview ny (516) 694-6700 6 operations operations dual cas two cas pins ( lcas and ucas ) are provided to give independent control of the 16 data-i/o pins (i/o0-15), with lcas corresponding to i/o0-7 and ucas corresponding to i/o8-15. for read or write cycles, the column address is latched on the first xcas falling edge. each xcas going low enables its corresponding i/ox pin with data associated with the column address latched on the first falling xcas edge. all address setup and hold parameters are referenced to the first falling xcas edge. the delay time from xcas low to valid data out (see parameter t c a c ) is measured form each individual xcas to its corresponding i/ox pin. in order to latch in a new column address, both xcas pins must be brought high. the column-precharge time (see parameter t c p ) is measured from the last xcas rising edge to the first xcas falling edge of the new cycle. keeping a column address valid while toggling xcas requires a minimum setup time, t c l c h . during t c l c h at least one xcas must be brought low before the other xcas is taken high. for early-write cycles, the data is latched on the first xcas falling edge. only the i/os that have the corresponding xcas low are written into. each xcas must meet t c a s minimum in order to ensure writing into the storage cell. to latch a new address and new data, all xcas pins must be high and meet t c p . page mode page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. the time for row-address setup and hold and address multiplex is eliminated. the maximum number of columns that can be accessed is determined by the maximum ras low time and the xcas page-mode cycle time used. with minimum xcas page-cycle time, all columns can be accessed without intervening ras cycles. unlike conventional page-mode drams, the column address buff-ers in this device are activated on the falling edge of ras . the buffers act as transparent or flow-through latches while xcas is high. the falling edge of the first xcas latches the column addresses. this feature allows the devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when xcas transitions low. this performance improvement is referred to as enhanced page mode. a valid column address may be presented immediately after t r a h (row-address hold time) has been satisfied, usually well in advance of the falling edge of xcas . in this case, data is obtained after t c a c maximum (access time from xcas low) if t a a maximum (access time from column address) has been satisfied. in the event that column addresses for the next page cycle are valid at the time xcas goes high, minimum access time for the next cycle is determined by t c p a (access time from rising edge of the last xcas ). address: a0-9 twenty address bits are required to decode 1 of 1048576 storage cell locations. for the actpd1m16, 10 row-address bits are set up on a0 through a9 and latched onto the chip by ras . ten, column-address bits are set up on a0 through a9 and latched onto the chip by the first xcas . all addresses must be stable on or before the falling edge of ras and xcas . ras is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xcas is used as a chip select, activating its correspond-ing output buffer and latching the address bits into the column-address buffers.
aeroflex circuit technology scd3750 rev a 8/31/98 plainview ny (516) 694-6700 7 write enable ( we ) the read or write mode is selected through we . a logic high on we selects the read mode and a logic low selects the write mode. the data inputs are disabled when the read mode is selected. when we goes low prior to xcas (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with oe grounded. data in (i/o 0-15 ) data is written during a write or read-modify-write cycle. depending on the mode of operation, the falling edge of xcas or we strobes data into the on-chip data latch. in an early-write cycle, we is brought low prior to xcas and the data is strobed in by the first occurring xcas with setup and hold times referenced to this signal. in a delayed-write or read-modify-write cycle, xcas is already low and the data is strobed in by we with setup and hold times referenced to this signal. in a delayed-write or read-modify-write cycle, oe must be high to bring the output buffers to the high-impedance state prior to impressing data on the i/o lines. data out (i/o 0-15 ) data out is the same polarity as data in. the output is in the high-impedance (floating) state until xcas and oe are brought low. in a read cycle, the output becomes valid after the access time interval t c a c (which begins with the negative transition of xcas ) as long as t r a c and t a a are satisfied. output enable ( oe )* oe controls the impedance of the output buffers. when oe is high, the buffers remain in the high-impedance state. bringing oe low during a normal cycle activates the output buffers, putting them in the low-impedance state. it is necessary for both ras and xcas to be brought low for the output butters to go into the low-impedance state, and they remain in the low-impedance state until either oe or xcas is brought high. *output enable can be held low during write cycles. ras -only refresh a refresh operation must be performed at least once every 16ms (128ms for long refresh periods) to retain data. this can be achieved by strobing each of the 1024 rows (a0-9). a normal read or write cycle refreshes all bits in each row that is selected. a ras -only operation can be used by holding both xcas at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. externally generated addresses must be used for a ras -only refresh. hidden refresh hidden refresh can be performed while maintaining valid data at the output pin. this is accomplished by holding xcas at v i l after a read operation and cycling ras after a specified precharge period, similar to a ras -only refresh cycle. the external address is ignored and the refresh address is generated internally. xcas -before- ras ( xcbr ) refresh xcbr refresh is utilized by bringing at least one xcas low earlier than ras (see parameter t c s r ) and holding it low after ras fails (see parameter t c h r ). for succesive xcbr refresh cycles, xcas can remain low while cycling ras . the external address is ignored and the refresh address is generated internally. power up to achieve proper device operation, an initial pause of 200s followed by a minimum of eight initialization cycles is required after power up to full vcc level. these eight initialization cycles must include at least one refresh ( ras -only or xcbr ) cycle.
aeroflex circuit technology scd3750 rev a 8/31/98 plainview ny (516) 694-6700 8 all dimensions in millimeters dimensions in inches () 9.40 (0.370) 0.25 (0.070) 3.51 (0.138) 0.25 (0.01) 27.30 (1.075) 0.13 (0.005) 11.18 (0.440) 0.13 (0.005) 1.27 (0.050) .46 (.018 2.69 (0.106) typ dimensions in millimeters mm 1 21 22 42 typ 0.05 0.002) typ pin 1 identifier (do not block with label) 10.16 (0.400) 0.13 (0.005) 0.20 (0.008) typ package outline "l4" ? soj package, 42 leads
aeroflex circuit technology scd3750 rev a 8/31/98 plainview ny (516) 694-6700 9 ordering information (typical) model number options speed package act-pd1m16n?070l4i none 70ns 42 lead soj act-pd1m16w?070l4i burn-in 70ns 42 lead soj act-pd1m16x?070l4i temp cycle 70ns 42 lead soj act-pd1m16y?070l4i temp cycle & burn-in 70ns 42 lead soj act-pd1m16n?070l4t none 70ns 42 lead soj act-pd1m16w?070l4t burn-in 70ns 42 lead soj act-pd1m16x?070l4t temp cycle 70ns 42 lead soj act-pd1m16y?070l4t temp cycle & burn-in 70ns 42 lead soj 070 = 70ns aeroflex circuit technology * screened to the test methods of mil-std-883 part number breakdown aeroflex circuit technology 35 south service road plainview new york 11830 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: 1-(800) 843-1553 circuit technology \\\ act- p d 1m 16 n? 070 l4 t memory type d = plastic dram memory depth, locations options memory width, bits n = none w = burn-in * x = temperature cycle * y = burn-in & temperature cycle * memory speed, ns package type & size l4 = 42 pin plastic soj electrical testing i = industrial temp, -40c to +85c t = military temp, -55c to +125c plastic path
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